What Is the Delay from DMA Request to DMA Acknowledge?

What Is the Delay from DMA Request to
DMA Acknowledge?

The amount of delay from when an I/O device requests a DMA transfer until the DMA completes the transfer—also known at the DMA transfer latency—depends on the transfer direction and the other activity on the CSI bus.

Figure 1, for example, shows a device-to-memory DMA transfer. The minimum latency from DMA request to acknowledge is four clock cycles. The minimum latency assumes that the DMA is granted the CSI bus when required and that there are no wait-states asserted during any of the interim non-DMA bus cycles.

Figure 1. Device-to-Memory Transfer Cycle Using DMA.

Similarly, Figure 2 shows a memory-to device DMA transfer. The minimum request-to-acknowledge time is seven cycles. The latency is longer than for a device-to-memory transfer because the DMA must first read from memory before writing to the device.

Figure 2. Memory-to-Device Transfer Cycle Using DMA.

The request-to-acknowledge latency might increase depending on other activity on the CSI bus. Multiple bus masters—such as the CPU, the DMA channels, and the JTAG controller—share the CSI bus and are granted the bus in a round-robin fashion. The latency may increase if the DMA requests the bus—either for the memory or device transfer—and is not immediately granted the bus. In the E5 and A7, there is no way to increase the arbitration priority of the DMA controller. Also, all DMA channels have effectively the same priority.

The latency may also increase if there are wait states during the non-DMA bus cycles between the request cycle, the memory transfer cycle, and the device transfer cycle.

Any un-serviced DMA requests are tracked by the DMA controller and serviced on a first-requested, first-served basis.